DocumentCode :
2039759
Title :
Verification of digital control paths using Petri nets
Author :
Erhard, Werner ; Reinsch, Andreas ; Schober, Torsten
Author_Institution :
Dept. of Comput. Sci., Jena Univ., Germany
Volume :
4
fYear :
2001
fDate :
2001
Firstpage :
2694
Abstract :
Introduces a hardware design methodology based on Petri nets that is applied to the verification of digital control paths. The main purpose is to design control paths that are modeled and verified formally by means of Petri net techniques. A verified digital system can be implemented in self-timed or in synchronous clocked hardware modules. Finally, timing analysis can be performed by timed Petri nets
Keywords :
Petri nets; control system CAD; control system analysis computing; digital control; digital systems; logic CAD; Petri nets; digital control paths; hardware design methodology; self-timed hardware modules; synchronous clocked hardware modules; timing analysis; verification; Clocks; Computer science; Design methodology; Digital control; Digital systems; Hardware; Modeling; Performance analysis; Petri nets; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Systems, Man, and Cybernetics, 2001 IEEE International Conference on
Conference_Location :
Tucson, AZ
ISSN :
1062-922X
Print_ISBN :
0-7803-7087-2
Type :
conf
DOI :
10.1109/ICSMC.2001.972973
Filename :
972973
Link To Document :
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