Implementation of a 64-bit Jackson adder

In 2004, Robert Jackson and Sunil Talwar published a novel method of decomposing binary prefix addition. Their work sought to balance the complexity of the generate and propagate terms that bear the computational load in parallel prefix adders. This paper presents an implementation of a 64-bit adder based on this method, as well as an improved method of expressing this complex decomposition. This adder is compared to the optimized Sklansky architecture produced by Design Compiler in a 45 nm process. The 64-bit Jackson adder is 5% faster than the DesignWare adder, but uses 80% more energy.