Title :
Proceedings. 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Abstract :
The following topics are dealt with: design patterns for reconfigurable computing; overview of the FREEDOM compiler for mapping DSP software to FPGAs; automated least-significant bit datapath optimization for FPGAs; a flexible hardware encoder for low-density parity-check codes; deep packet filter with dedicated logic and read only memories; register binding for FPGAs with embedded memory; scalable pattern matching for high speed networks; word-length optimization of folded polynomial evaluation; hyperreconfigurable architectures for fast run time reconfiguration using FIFOs in hardware-software co-design for FPGA based embedded systems; power management for FPGAs: power- driven design partitioning.
Keywords :
digital signal processing chips; electronic engineering computing; embedded systems; encoding; field programmable gate arrays; filtering theory; hardware-software codesign; memory architecture; optimisation; parity check codes; pattern matching; polynomials; program compilers; read-only storage; reconfigurable architectures; DSP software; FIFO; FPGA; FREEDOM compiler; deep packet filter; embedded memory; embedded systems; field programmable custom computing machines; flexible hardware encoder; hardware software co-design; high speed networks; least significant bit datapath; low density parity check codes; polynomial evaluation; power management; read only memories; reconfigurable computing; register binding; run time reconfiguration; scalable pattern matching; word length optimization;
Conference_Titel :
Field-Programmable Custom Computing Machines, 2004. FCCM 2004. 12th Annual IEEE Symposium on
Conference_Location :
Napa, CA, USA
Print_ISBN :
0-7695-2230-0
DOI :
10.1109/FCCM.2004.57
