Title :
A built-in self-test circuit with timing margin test function in a 1 Gbit synchronous DRAM
Author :
Sakashita, Narumi ; Okuda, Fumihiro ; Shimomura, Ken´ichi ; Shimano, Hiroki ; Hamada, Mitsuhiro ; Tada, Tetsuo ; Komori, Shinji ; Kyuma, Kazuo ; Yasuoka, Akihiko ; Abe, Haruhiko
Author_Institution :
Adv. Technol. R&D Center, Mitsubishi Electr. Corp., Itami, Japan
Abstract :
This paper describes the implementation of a BIST circuit with timing margin test functions to a 200 MHz 1 Gbit synchronous DRAM. 220 ps-resolution timing signals with up to 80 ns cycle time are generated by a phase-locked loop (PLL) circuit and a delayed timing generator. These timing signals are used not only as actual control signals but also as reference signals in an AC timing comparator. The entire BIST circuit, which includes 20×4 bit LFSRs, occupies only 0.8% of the chip area. A cost evaluation of the BIST shows that the technology is effective for 64 Mbit high-speed DRAMs and beyond
Keywords :
DRAM chips; automatic testing; built-in self test; integrated circuit testing; timing; 200 MHz; 220 ps; 64 Mbit to 1 Gbit; 80 ns; AC timing comparator; BIST circuit; LFSR; PLL circuit; built-in self-test; delayed timing generator; dynamic RAM; high-speed DRAMs; phase-locked loop; reference signals; synchronous DRAM; timing margin test function; AC generators; Built-in self-test; Circuit testing; Clocks; Costs; Delay; Frequency; Phase locked loops; Signal generators; Timing;
Conference_Titel :
Test Conference, 1996. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-3541-4
DOI :
10.1109/TEST.1996.556977
