Development of board level simulation models of complex standard components

VHDL is rapidly becoming the design language of choice for ASIC design courses which make use of logic synthesis tools. It is often desirable to simulate student designs embedded in a more complete system which may be composed of a microprocessor, RAM, ROM and other standard components as well as the student´s ASIC. A bus functional model is more efficient than an equivalent gate level model and is an attractive alternative for system level simulation. This paper details the development of bus functional VHDL models for a system containing a digital signal processor (ADSP-21020), SRAMs (IDT71024), an FPGA used as an SBus interface (XC4013), and two FPGAs that are user reconfigurable (XC4010). The system is a reconfigurable coprocessor board (Chameleon Coprocessor) under development for the Sun workstation