• DocumentCode
    2040781
  • Title

    Path-based cell flipping optimization for wirelength reduction and routability

  • Author

    Shih, Ying-An ; Tsai, Tu-Hsiung ; Chen, Hung-Ming

  • Author_Institution
    Integrated Circuit Dept. III, RDC Semicond. Co., Ltd., Hsinchu, Taiwan
  • fYear
    2010
  • fDate
    21-24 Nov. 2010
  • Firstpage
    1535
  • Lastpage
    1539
  • Abstract
    Wirelength reduction is always a concern in almost every methodology in physical design optimization. A recent study shows that solving cell flipping optimally can further reduce wirelength without affecting the original placement solution. In practical observation, there are still a lot of placed standard 2-pin logic cells which can be further mirrored to decrease the total routing length. In this work, we provide a path-based optimization methodology that can be applied before detailed routing, and this will help the router to improve the final routing length. This method can also be easily applied in the ECO stage to prevent the wire crossing effects, without impacting the local routability. A number of real industry tape-out cases are experimented to illustrate the effectiveness of the proposed methodology and to get shorter wirelength.
  • Keywords
    circuit CAD; logic arrays; network routing; 2-pin logic cells; path-based cell flipping optimization; physical design optimization; wire crossing effects; wirelength reduction; wirelength routability;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    TENCON 2010 - 2010 IEEE Region 10 Conference
  • Conference_Location
    Fukuoka
  • ISSN
    pending
  • Print_ISBN
    978-1-4244-6889-8
  • Type

    conf

  • DOI
    10.1109/TENCON.2010.5686148
  • Filename
    5686148