Title :
VHDL implementation of high performance RC6 algorithm using ancient Indian vedic mathematics
Author :
Moses, S.L.G. ; Thilagar, M.
Author_Institution :
VLSI Design, Adhiparsakthi Eng. Coll., Melmaruvathur, India
Abstract :
RC6 is the successor to RC5. It is one of the most promising algorithms that is both fast and secure. It uses four w-bit registers, integer multiplication, quadratic equation and fixed bit shifting. This paper examines how the Vedic algorithm of Urdhva tiryagbhyam speeds up the computation of this algorithm when compared with conventional algorithms in existence.
Keywords :
algorithm theory; cryptography; hardware description languages; mathematics computing; RC5; VHDL implementation; ancient Indian vedic mathematics; fixed bit shifting; high performance RC6 algorithm; integer multiplication; quadratic equation; urdhva tiryagbhyam; vedic algorithm; w-bit register; Algorithm design and analysis; Clocks; Educational institutions; Encryption; Power dissipation; Registers; RC6; Urdhva Tiryagbhyam;
Conference_Titel :
Electronics Computer Technology (ICECT), 2011 3rd International Conference on
Conference_Location :
Kanyakumari
Print_ISBN :
978-1-4244-8678-6
Electronic_ISBN :
978-1-4244-8679-3
DOI :
10.1109/ICECTECH.2011.5941874
