FPGA-based implementation of a robust IEEE-754 exponential unit

Author

Doss, Christopher C. ; Riley, Robert L.

Author_Institution

Dept. of Electr. & Comput. Eng., North Carolina A&T State Univ., Greensboro, NC, USA

fYear

2004

fDate

20-23 April 2004

Firstpage

229

Lastpage

238

Abstract

This work explores the feasibility of implementing a floating-point exponentiation unit on reconfigurable computing systems. A table-driven exponentiation unit was implemented using synthesizable VHDL. The project included creating pipelined submodules for implementing basic IEEE-754 single precision operations such as addition, multiplication, and division by 32. These modules were then linked together to form the overall unit. The designs were synthesized, placed and routed. Results indicate that today´s FPGAs are well suited for this operation.

Keywords

IEEE standards; field programmable gate arrays; floating point arithmetic; hardware description languages; logic design; pipeline arithmetic; reconfigurable architectures; FPGA based implementation; VHDL; floating point exponentiation unit; logic design; pipelined submodules; reconfigurable computing systems; robust IEEE-754 exponential unit; table driven exponentiation unit; Field programmable gate arrays; Floating-point arithmetic; Hardware; Laboratories; Libraries; Military computing; Performance gain; Programmable logic devices; Robustness; Weapons;

fLanguage

English

Publisher

ieee

Conference_Titel

Field-Programmable Custom Computing Machines, 2004. FCCM 2004. 12th Annual IEEE Symposium on

Print_ISBN

0-7695-2230-0

Type

conf

DOI

10.1109/FCCM.2004.38

Filename

1364633