Design of an on-line IEEE floating-point addition unit for FPGAs

We present the design of an on-line IEEE floating-point (FP) adder. In on-line arithmetic a result is computed as a digit serial output stream from digit serial input streams. The result digits begin to be produced a short delay after the first input digits arrive and before all the input digits have been received. On-line arithmetic proceeds from the most significant digit first through the least significant digit. Performing on-line addition on IEEE FP numbers imposes challenges beyond the challenges of conventional on-line arithmetic, including the task of normalization and IEEE rounding and its effect on the digits already output. The proposed implementations are very suitable for FPGAs, because the serial organization simplifies critical components of conventional FPGA IEEE FP addition implementations: Large alignment and normalization shifters are avoided allowing for reduced interconnection complexities and reasonable latencies at low implementation cost. The proposed implementations are fully compliant with the IEEE FP standard.