500MSPS with 80dB SFDR SHA for Time interleaved application using LATERAL PNP in CMOS process

In this work, a SHA technique is presented, with modifications to core OTA. Precharging the flip around sample and hold output speeds up the settling behavior of the OTA. Modifications to the OTA make it possible to achieve the specifications with much lower power dissipation than a conventional OTA of the same type. Using this technique along with Op-Amp sharing, a 500 MSPS SHA with 80 dB Spurious Free Dynamic Range (SFDR) and 2.5 mW power dissipation is implemented in 0.18 ¿m technology. The proposed modification to the OTA can be applied in other types of switch capacitors circuits, such as gain stages, to reduce power dissipation while maintaining other specification.