DocumentCode
2041399
Title
The MOLEN processor prototype
Author
Kuzmanov, Georgi ; Gaydadjiev, Georgi ; Vassiliadis, Stamatis
Author_Institution
Comput. Eng. Lab., EEMCS, TU Delft, Netherlands
fYear
2004
fDate
20-23 April 2004
Firstpage
296
Lastpage
299
Abstract
We present a prototype design of the MOLEN polymorphic processor, a CCM based on the co-processor architectural paradigm. The Xilinx Virtex II Pro technology is used as a prototyping platform. Experimental results prove the viability of the MOLEN concept. More precisely, the MPEG-2 application is accelerated very closely to its theoretical limits by implementing SAD, DCT and IDCT in reconfigurable hardware. The MPEG-2 encoder overall speedup is in the range between 2.80 and 2.96. The speedup of the MPEG-2 decoder varies between 1.56 and 1.63.
Keywords
coprocessors; discrete cosine transforms; encoding; field programmable gate arrays; reconfigurable architectures; software prototyping; DCT; MOLEN polymorphic processor; MPEG-2 decoder; MPEG-2 encoder; Xilinx Virtex II Pro technology; coprocessor architecture; prototype design; reconfigurable hardware; sum of absolute differences; Acceleration; Coprocessors; Decoding; Design engineering; Discrete cosine transforms; Explosions; Field programmable gate arrays; Hardware; Prototypes; Registers;
fLanguage
English
Publisher
ieee
Conference_Titel
Field-Programmable Custom Computing Machines, 2004. FCCM 2004. 12th Annual IEEE Symposium on
Print_ISBN
0-7695-2230-0
Type
conf
DOI
10.1109/FCCM.2004.55
Filename
1364648
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