FPGA based embedded processing architecture for the QRD-RLS algorithm

Author

Boppana, Deepak ; Dhanoa, Kully ; Kempa, Jesse

Author_Institution

Altera Corp., San Jose, CA, USA

fYear

2004

fDate

20-23 April 2004

Firstpage

330

Lastpage

331

Abstract

A novel implementation of the QR decomposition based recursive least squares (RLS) algorithm on Altera Stratix FPGAs is presented. CORDIC (coordinate rotation by digital computer) operators are efficiently time-shared to perform the QR decomposition while consuming minimal resources. Back substitution is then performed on the embedded soft Nios processor by utilizing custom instructions to yield the final weight vectors. Analytical resource estimates along with actual implementation results illustrating the weight calculation delays are also presented.

Keywords

digital arithmetic; field programmable gate arrays; least mean squares methods; matrix decomposition; recursive estimation; signal processing; systolic arrays; Altera Stratix FPGA; CORDIC; FPGA based embedded processing architecture; QR decomposition based recursive least squares; QRD RLS algorithm; coordinate rotation digital computer; custom instructions; embedded soft Nios processor; weight calculation; Delay estimation; Equations; Field programmable gate arrays; Hardware; Least squares methods; Matrices; Matrix decomposition; Signal processing algorithms; Systolic arrays; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Field-Programmable Custom Computing Machines, 2004. FCCM 2004. 12th Annual IEEE Symposium on

Print_ISBN

0-7695-2230-0

Type

conf

DOI

10.1109/FCCM.2004.34

Filename

1364663