Automating the layout of reconfigurable subsystems via template reduction

The focus of this work is the automatic generation of mask layouts, which is performed by the VLSI layouts, which is performed by the VLSI generator. This paper also presents method of automating the layout process, the template reduction method. The goal of the template reduction is not only the removal of unneeded routing resource, but also the removal of unneeded functional units. Benchmarking results show that template reduction method is able to reduce the number of functional units by an average of 45% and the routing resources by an average of 75%. It is found that the template reduction method produces circuits that are on average 53.4% smaller and 13.9% faster than the unreduced template.