Title :
Reduced TCP/IP Protocol Implement in VHDL
Author :
Wang Renbo ; Wei Xiong
Author_Institution :
Dept. of Electron. Eng., East China Inst. of Technol., Fuzhou
Abstract :
This paper describes the design and implement of a simple reduced TCP/IP protocol stack in VHDL that can be used in a soft-core embedded system (SOPC system) to establish high speed link between remote terminals and host. This is a significative experimental project whose target is high performance for image transmission with lower possession of CPU resource of embedded system.
Keywords :
embedded systems; hardware description languages; transport protocols; CPU resource; TCP/IP protocol stack; VHDL; reduced TCP/IP protocol; soft-core embedded system; Central Processing Unit; Cyclic redundancy check; Design engineering; Embedded system; Ethernet networks; Field programmable gate arrays; Hardware; Image communication; Protocols; TCPIP;
Conference_Titel :
Intelligent Systems and Applications, 2009. ISA 2009. International Workshop on
Conference_Location :
Wuhan
Print_ISBN :
978-1-4244-3893-8
Electronic_ISBN :
978-1-4244-3894-5
DOI :
10.1109/IWISA.2009.5073030
