Title :
A VHDL approach to system design for multiprocessor circuit simulation
Author :
Wu, K.Y. ; Chen, R.M.M. ; Cheng, L.M. ; Fong, A.S.
Author_Institution :
Dept. of Electron. Eng., City Polytech. of Hong Kong, Kowloon, Hong Kong
Abstract :
For the execution of a large circuit simulation problem on a bus-based master-slave multiprocessor system with shared memory, increasing the number of tasks does not always decrease the execution time. The tradeoff between communication and parallelism will have direct effect on the computation performance. To assess the performance of such a system, a behavioral simulation of its architecture is presented using the VHSIC Hardware Description Language (VHDL). The behavioral model will enable the evaluation of the multiprocessor system design and to assess algorithm-to-architecture mapping.<>
Keywords :
VLSI; circuit analysis computing; shared memory systems; specification languages; VHDL approach; VHSIC Hardware Description Language; algorithm-to-architecture mapping; behavioral simulation; computation performance; multiprocessor circuit simulation; parallelism; shared memory system; system design; Algorithm design and analysis; Circuit simulation; Computational modeling; Computer architecture; Concurrent computing; Hardware design languages; Master-slave; Multiprocessing systems; Parallel processing; Very high speed integrated circuits;
Conference_Titel :
TENCON '93. Proceedings. Computer, Communication, Control and Power Engineering.1993 IEEE Region 10 Conference on
Conference_Location :
Beijing, China
Print_ISBN :
0-7803-1233-3
DOI :
10.1109/TENCON.1993.320215
