Title :
Detecting delay flaws by very-low-voltage testing
Author :
Chang, Jonathan T -Y ; McCluskey, Edward J.
Author_Institution :
Center for Reliable Comput., Stanford Univ., CA, USA
Abstract :
The detectability of delay flaws can be improved by testing CMOS IC´s with a very low supply voltage-between 2 and 2.5 times the threshold voltage Vt of the transistors. A delay flaw is a defect that causes a local timing failure but the failure is not severe enough to cause malfunctioning. Delay flaws caused by degraded signals and gates with lower drive capability than expected are considered. This paper investigates the voltage dependence of the effects of delay flaws and derives the test conditions for them
Keywords :
CMOS digital integrated circuits; circuit analysis computing; delays; digital simulation; integrated circuit testing; logic testing; CMOS IC; degraded signals; delay flaw; delay flaws; detectability; drive capability; local timing failure; malfunctioning; propagation delays; very-low-voltage testing; voltage dependence; CMOS integrated circuits; Circuit faults; Circuit testing; Degradation; Delay; Electrical fault detection; Fault detection; MOSFETs; Threshold voltage; Timing;
Conference_Titel :
Test Conference, 1996. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-3541-4
DOI :
10.1109/TEST.1996.556983
