Title :
Efficient design for transistor level and function
Author :
Deepmala, Km ; Sharma, Tripti ; Sharma, K.G. ; Singh, B.P.
Author_Institution :
FET, Dept. of ECE, MITS, Lakshmangarh, India
Abstract :
This paper proposes a new design of 2T AND gate. All the designs are compared with respect to the transistor count, power consumption, temperature sustain ability, noise immunity and parasitic capacitance in order to prove the superiority of proposed design over existing designs. The pre layout simulation has been carried out on BSIM3v3 90nm technology and post layout simulation has been performed on 0.5 submicron technology using Tanner EDA tool.
Keywords :
logic design; logic gates; transistor circuits; 2T AND gate design; BSIM3v3 technology; Tanner EDA tool; noise immunity; parasitic capacitance; power consumption; prelayout simulation; size 90 nm; submicron technology; temperature sustainability; transistor level AND function; CMOS integrated circuits; CMOS technology; Integrated circuit modeling; Logic gates; MOS devices; Power demand; Transistors; AND gate; CMOS; Low power; PDP; PTL and GDI technique;
Conference_Titel :
Electronics Computer Technology (ICECT), 2011 3rd International Conference on
Conference_Location :
Kanyakumari
Print_ISBN :
978-1-4244-8678-6
Electronic_ISBN :
978-1-4244-8679-3
DOI :
10.1109/ICECTECH.2011.5941925
