• DocumentCode
    2042202
  • Title

    DSP Implementation of Deblocking Filter for AVS

  • Author

    Yang, Zhigang ; Gao, Wen ; Liu, Yan ; Zhao, Debin

  • Author_Institution
    Harbin Inst. of Technol., Harbin
  • Volume
    6
  • fYear
    2007
  • fDate
    Sept. 16 2007-Oct. 19 2007
  • Abstract
    The in-loop deblocking filter contains highly adaptive processing on both sample level and block edge level, which inevitably appears in the loop kernel of the algorithm. Therefore it is a challenge for parallel processing on a digital signal processor (DSP) platform. In this paper, pipelined DSP solutions to the in-loop deblocking filter in AVS1-P2 are presented. First, the whole filter process is divided into six sub-processes, so that the global filter structure can be improved to achieve regular processing flow. Then software pipelines are designed for these sub-processes, with elaborately allocating functional units and carefully choosing enhanced assembly instructions based on the DSP platform. The simulated results show that this efficient implementation can easily support real-time filter processing for high resolution videos.
  • Keywords
    digital signal processing chips; filtering theory; image resolution; parallel processing; pipeline processing; video signal processing; audio video standard; digital signal processor platform; high resolution video; in-loop deblocking filter; parallel processing; Adaptive filters; Assembly; Digital signal processing; Digital signal processors; Kernel; Parallel processing; Pipelines; Signal processing algorithms; Software design; Videos; AVS; Pipelines; deblocking filter; digital signal processors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Image Processing, 2007. ICIP 2007. IEEE International Conference on
  • Conference_Location
    San Antonio, TX
  • ISSN
    1522-4880
  • Print_ISBN
    978-1-4244-1437-6
  • Electronic_ISBN
    1522-4880
  • Type

    conf

  • DOI
    10.1109/ICIP.2007.4379557
  • Filename
    4379557