DocumentCode
2043464
Title
Parallel FPGA-based all-pairs shortest-paths in a directed graph
Author
Bondhugula, Uday ; Devulapalli, Ananth ; Fernando, Joseph ; Wyckoff, Pete ; Sadayappan, P.
Author_Institution
Dept. of Comput. Sci. & Eng., Ohio State Univ., Columbus, OH, USA
fYear
2006
fDate
25-29 April 2006
Abstract
With rapid advances in VLSI technology, field programmable gate arrays (FPGAs) are receiving the attention of the parallel and high performance computing community. In this paper, we propose a highly parallel FPGA design for the Floyd-Warshall algorithm to solve the all-pairs shortest-paths problem in a directed graph. Our work is motivated by a computationally intensive bio-informatics application that employs this algorithm. The design we propose makes efficient and maximal utilization of the large amount of resources available on an FPGA to maximize parallelism in the presence of significant data dependences. Experimental results from a working FPGA implementation on the Cray XD1 show a speedup of 22 over execution on the XD1´s processor.
Keywords
directed graphs; field programmable gate arrays; parallel algorithms; Cray XD1 processor; Floyd-Warshall algorithm; VLSI technology; all-pair shortest-path problem; bioinformatics application; directed graph; field programmable gate array; high performance computing; parallel FPGA design; parallel computing; very large scale integration; Algorithm design and analysis; Application software; Bonding; Design optimization; Field programmable gate arrays; High performance computing; Parallel processing; Signal processing algorithms; Supercomputers; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel and Distributed Processing Symposium, 2006. IPDPS 2006. 20th International
Print_ISBN
1-4244-0054-6
Type
conf
DOI
10.1109/IPDPS.2006.1639347
Filename
1639347
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