Multi-clock domain optimization for reconfigurable architectures in high-level dataflow applications

This paper proposes a new design methodology to partition streaming applications onto a multi clock domain architecture. The objective is to save power by running different parts of the application at the lowest possible clock frequency that will not violate the throughput requirements. The solution involves partitioning the application into an appropriate number of clock domains, and then assigning each of those domains a clock frequency. Two different approaches are illustrated, both based on the post-processing and analysis of the causation trace of a dataflow program. Methodology and initial experimental results are demonstrated in an at-size scenario using an MPEG-4 Simple Profile decoder implemented in a FPGA platform.