Title :
A floating-point validation suite for high-performance shared and distributed memory computing systems
Author_Institution :
Supercomput. Educ. & Res. Centre, Indian Inst. of Sci., Bangalore, India
Abstract :
A methodology to systematically identify and isolate bugs in floating point implementation in high performance multiple CPU computing systems is formulated. A validation suite is written and tested. Results show improper implementation. Proper implementation guidelines are suggested and prototyped
Keywords :
distributed memory systems; floating point arithmetic; parallel programming; program verification; shared memory systems; distributed memory computing systems; floating point implementation; floating point validation suite; high performance multiple CPU computing systems; high performance shared memory computing systems; validation suite; Central Processing Unit; Computer bugs; Distributed computing; Error correction; Floating-point arithmetic; Hardware; High performance computing; Supercomputers; System software; Testing;
Conference_Titel :
High-Performance Computing, 1997. Proceedings. Fourth International Conference on
Conference_Location :
Bangalore
Print_ISBN :
0-8186-8067-9
DOI :
10.1109/HIPC.1997.634476
