DocumentCode
2044496
Title
Design automation for a 2 /spl mu/m CMOS gate array
Author
Chua Hong-Chuek
Author_Institution
Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore
Volume
4
fYear
1993
fDate
19-21 Oct. 1993
Firstpage
347
Abstract
This paper presents specific technical information on the development of a design automation system for a 2 /spl mu/m double-metal CMOS gate array. It highlights the physical database requirements of a workstation-based design system and focuses on the features that facilitate the development of the design system and enhance the system´s performance efficiency. Some possible pitfalls that should be avoided are also discussed.<>
Keywords
CMOS integrated circuits; application specific integrated circuits; circuit CAD; integrated circuit design; logic CAD; logic arrays; ASIC; IC design; database requirements; design automation; double-metal CMOS gate array; logic CAD; performance efficiency; workstation-based design system; CMOS digital integrated circuits; Databases; Design automation; Flip-flops; Floors; MOS devices; Metallization; Process design; Routing; Variable structure systems;
fLanguage
English
Publisher
ieee
Conference_Titel
TENCON '93. Proceedings. Computer, Communication, Control and Power Engineering.1993 IEEE Region 10 Conference on
Conference_Location
Beijing, China
Print_ISBN
0-7803-1233-3
Type
conf
DOI
10.1109/TENCON.1993.320503
Filename
320503
Link To Document