Low power design techniques applied to pipelined parallel and iterative CORDIC design

CORDIC (COrdinate Rotation for Digital Computers) is a hardware efficient algorithm that can be used for the implementation of all kinds of digital signal processing architectures used in most of the processing instruments. Today, for most electronic designs, power budget is one of the most important design goals. The paper analyses clock-gating technique, a simple method for power reduction, applied to the different CORDIC architectures and compares their performance especially in three different major styles iterative, parallel and pipelined structures. The core is designed in VHDL, simulated using Modelsim simulator and Implemented using Xilinx FPGA synthesis and Synopsis ASIC synthesis tools.