Title :
Analysis of breakdown voltage and on resistance of super junction power MOSFET CoolMOSTM using theory of novel voltage sustaining layer
Author :
Kondekar, P.N. ; Parikh, C.D. ; Patil, M.B.
Author_Institution :
Dept. of Electr. Eng., Indian Inst. of Technol., Bombay, India
Abstract :
Conventional VDMOS (vertically double diffused metal oxide semiconductor) Technology for power devices was constrained by the Silicon Limit. This is now improved to have a linear relation between on resistance (Ron) and breakdown voltage (BV) instead of the quadratic relation. Theory of novel voltage sustaining layers (SJ-theory) recently published analytically models the super junction drift layers (SJ-drift layer). The authors have designed SJ-layers based on this theory and used to construct the SJ-MOSFET: CoolMOS structure. The claim of the theory that the doping level in the drift layer can now be increased by at least me order of magnitude without lowering BV is analyzed in detail. With the new silicon limit, one now can increase BV of a power device, just by increasing thickness of the SJ-drift layer. R on and BV relationship as the thickness of the device varies is analyzed with the help of simulation. The limitations and constraints of applying SJ-theory for the CoolMOS structure are discussed. The SJ- theory does not model the behavior of Ron and BV for a fixed geometry as doping level changes. The authors observed that for a fixed geometry the rate of reduction of the BV depends on the cell pitch. This rate is large for the higher cell pitch. The effect of charge imbalance created due the channel region in CoolMOS is also investigated
Keywords :
p-n junctions; power MOSFET; semiconductor device models; semiconductor doping; breakdown voltage; cell pitch; channel region; charge imbalance; doping level; on resistance; silicon limit; simulation; super junction drift layers; super junction power MOSFET CoolMOSTM; voltage sustaining layer theory; Doping; Electric resistance; Geometry; MOSFET circuits; Microelectronics; Power MOSFET; Semiconductor process modeling; Silicon; Student members; Voltage;
Conference_Titel :
Power Electronics Specialists Conference, 2002. pesc 02. 2002 IEEE 33rd Annual
Conference_Location :
Cairns, Qld.
Print_ISBN :
0-7803-7262-X
DOI :
10.1109/PSEC.2002.1023067