Title :
Proceedings 2005. 42nd Design Automation Conference (IEEE Cat. No. 05CH37676)
Abstract :
Presents the front cover of the conference proceedings.
Keywords :
analogue integrated circuits; boundary-elements methods; circuit optimisation; cryptography; design for manufacture; design for testability; electronic design automation; embedded systems; fault tolerance; field programmable gate arrays; formal verification; high level synthesis; logic design; mixed analogue-digital integrated circuits; reconfigurable architectures; reduced order systems; statistical analysis; system-on-chip; DFM rules; analog macromodeling; boundary element method; cryptography; design automation; design-for-testability method; embedded software; error-tolerant design; fault-toleran; high-level synthesis; leakage analysis; microarchitecture-level power analysis; optimization technique; parasitic extraction; signal integrity; statistical timing analysis;
Conference_Titel :
Design Automation Conference, 2005. Proceedings. 42nd
Conference_Location :
Anaheim, CA
Print_ISBN :
1-59593-058-2
DOI :
10.1109/DAC.2005.193736
