Exploring the implementation of JPEG compression on FPGA

Author

De Silva, Anthony Mihirana ; Bailey, Donald G. ; Punchihewa, Amal

Author_Institution

Sch. of Eng. & Adv. Technol., Massey Univ., Palmerston North, New Zealand

fYear

2012

fDate

12-14 Dec. 2012

Firstpage

1

Lastpage

9

Abstract

This paper presents the implementation of the JPEG compression on a field programmable gate array as the data are streamed from the camera. The goal was to minimise the logic resources of the FPGA and the latency at each stage of compression. The modules of these architectures are fully pipelined to enable continuous operation on streamed data. The designed architectures are detailed in this paper and they were described in Handel-C. The compliance of each JPEG module was validated using MATLAB. The resulting JPEG compressor has a latency of 8 rows of image readout plus 154 clock cycles.

Keywords

C language; cameras; discrete cosine transforms; field programmable gate arrays; image coding; pipeline processing; Handel-C; JPEG compression; JPEG compressor; JPEG module; MATLAB; camera; clock cycles; data streaming; designed architectures; discrete cosine transform; field programmable gate array; image readout; logic resources; pipeline architecture; DCT; FPGA; Handel-C; Huffman Coding; Image Compression; JPEG; Quantization; Zigzag;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing and Communication Systems (ICSPCS), 2012 6th International Conference on

Conference_Location

Gold Coast, QLD

Print_ISBN

978-1-4673-2392-5

Electronic_ISBN

978-1-4673-2391-8

Type

conf

DOI

10.1109/ICSPCS.2012.6508008

Filename

6508008