A dynamically reconfigurable deblocking filter for H.264/AVC codec

This paper introduces a dynamically reconfigurable implementation of deblocking filtering for H.264/AVC coding. The basic idea is to use a scalable approach that allows dynamic hardware reconfiguration of different modes based on power (or hardware complexity), bitrate, and image reconstruction quality. The modes are arranged hierarchically. A complex mode includes all of the deblocking filtering options of simpler modes. This provides scalable performance where the use of additional hardware resources (or power) result in better rate-distiortion performance. Within each mode, the deblocking filter is selected based on boundary strength so as to balance computational complexity with performance improvement. An optimal mode approach is also introduced. In the optimal mode, the mode with the best reconstruction quality is selected for each video frame. The optimal mode provides an upper bound (in the rate-distortion sense) to what can be achieved with the current modes. The deblocking filters are implemented on a Virtex-5 FPGA. The results are validated over 11 commonly-used videos, where image quality is assessed using SSIM.