Mapping DSP applications on processor systems with coarse-grain reconfigurable hardware

In this paper, we present performance results from mapping five real-world DSP applications on an embedded system-on-chip that incorporates coarse-grain reconfigurable logic with an instruction-set processor. The reconfigurable logic is realized by a 2-dimensional array of processing elements. A mapping flow for improving application´s performance by accelerating critical software parts, called kernels, on the coarse-grain reconfigurable array is proposed. Profiling is performed for detecting critical kernel code. For mapping the detected kernels on the reconfigurable logic a priority-based mapping algorithm has been developed. The experiments for three different instances of a generic system show that the speedup from executing kernels on the reconfigurable array ranges from 9.9 to 151.1, with an average value of 54.1, relative to the kernels´ execution on the processor. Important overall application speedups, due to the kernels´ acceleration, have been reported for the five applications. These overall performance improvements range from 1.3 to 3.7, with an average value of 2.3, relative to an all-software execution.