DocumentCode :
2046409
Title :
VoC: a reconfigurable matrix for stereo vision processing
Author :
Jacobi, Ricardo P. ; Cardoso, Renato B. ; Borges, Geovany A.
Author_Institution :
Dept. of Comput. Sci., Brasilia Univ.
fYear :
2006
fDate :
25-29 April 2006
Abstract :
This paper presents a reconfigurable matrix VoC that can be applied to stereo vision computation. VoC accelerates block pixel matching by providing a highly parallel implementation of the sum of absolute differences metric. Reconfigurability allows VoC to deal with different block sizes, ranging from a single 7 times 7 SAD computation to 9 simultaneous 5 times 5 block computations. The pipelined version mapped to Xilinx FPGA could be simulated at 158 MHz, producing 1.42 billion matching per second
Keywords :
field programmable gate arrays; reconfigurable architectures; stereo image processing; system-on-chip; 158 MHz; VoC; Xilinx FPGA; absolute differences metric; block pixel matching; reconfigurable matrix; stereo vision computation; stereo vision processing; Acceleration; Application software; Application specific integrated circuits; Application specific processors; Computer vision; Correlation; Field programmable gate arrays; Hardware; Jacobian matrices; Stereo vision;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Parallel and Distributed Processing Symposium, 2006. IPDPS 2006. 20th International
Conference_Location :
Rhodes Island
Print_ISBN :
1-4244-0054-6
Type :
conf
DOI :
10.1109/IPDPS.2006.1639454
Filename :
1639454
Link To Document :
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