DocumentCode
2046490
Title
A combined feasibility and performance macromodel for analog circuits
Author
Ding, Mengmeng ; Vemuri, Ranga
Author_Institution
Dept. of Electr. Comput. & Eng. Comput. Sci., Univ. of Cincinnati, OH, USA
fYear
2005
fDate
13-17 June 2005
Firstpage
63
Lastpage
68
Abstract
The need to reuse the performance macromodels of an analog circuit topology challenges existing regression based modeling techniques. A model of good reusability should have a number of independent design parameters and each parameter can vary in a large numeric range. On the other hand, these requirements can cause a large percentage of functionally incorrect designs in the design space and thus results in a sparse feasible design space. They also complicate the mathematical relationship between the performance parameters and the design parameters. In order to tackle these challenges, this paper presents a combined feasibility and performance macromodel based on support vector machines (SVMs). The feasibility model identifies the feasible designs that satisfy the design constraints. The performance macromodel is valid for feasible designs. Feasibility macromodeling is formulated as a classification problem while performance macromelting as a regression problem. An active learning scheme (Ding, et al., 2005) has been applied to improve the accuracy of the feasibility model much faster than only using uniformly distributed designs in the entire design space. The experiment of the authors showed that the performance macromodels in the feasible design space are more accurate and faster to construct and evaluate than performance macromodels in the entire design space without functional or performance constraints considered.
Keywords
analogue integrated circuits; circuit simulation; integrated circuit design; integrated circuit modelling; network topology; support vector machines; active learning scheme; analog circuit feasibility-performance macromodel; analog circuit topology; regression problem; reusability; support vector machines; Algorithm design and analysis; Analog circuits; Circuit simulation; Circuit topology; Equations; Force sensors; Integrated circuit modeling; Permission; Support vector machine classification; Support vector machines;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2005. Proceedings. 42nd
Print_ISBN
1-59593-058-2
Type
conf
DOI
10.1109/DAC.2005.193774
Filename
1510293
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