DocumentCode :
2046622
Title :
Platform-based FPGA architecture: designing high-performance and low-power routing structure for realizing DSP applications
Author :
Siozios, K. ; Tatas, K. ; Soudris, D. ; Thanailakis, A.
Author_Institution :
Dept. of Electr. & Comput. Eng., Democritus Univ. of Thrace, Xanthi, Greece
fYear :
2006
fDate :
25-29 April 2006
Abstract :
The novel design of an efficient FPGA interconnection architecture with multiple switch boxes (SB) and hardwired connections for realizing data intensive applications (i.e. DSP applications), is introduced. For that purpose, after exhaustive exploration, we modify the routing architecture through efficient selection of the appropriate switch box with hardwired connections, taking into account the statistical and spatial routing restrictions of DSP applications mapped onto FPGA. More specifically, we propose a new technique for selecting the appropriate combination of switch boxes, depending on the localized performance and power consumption requirements of each specific region of FPGA architecture. In order to perform the mapping, we developed a novel algorithm, which takes into account the modified architectural routing features. This algorithm was implemented within a new tool called EX-VPR. Using a number of DSP applications, extensive comparison study of various combinations of switch boxes in terms of total power consumption, performance, Powerx Delay product prove the effectiveness of the proposed approach.
Keywords :
digital signal processing chips; field programmable gate arrays; logic design; network routing; DSP application; FPGA interconnection architecture; multiple switch boxes; platform-based FPGA architecture; routing structure; spatial routing restriction; statistical routing restriction; Application software; Computer architecture; Digital signal processing; Energy consumption; Field programmable gate arrays; Logic; Routing; Switches; Testing; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Parallel and Distributed Processing Symposium, 2006. IPDPS 2006. 20th International
Print_ISBN :
1-4244-0054-6
Type :
conf
DOI :
10.1109/IPDPS.2006.1639462
Filename :
1639462
Link To Document :
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