Synthesized transparent BIST for detecting scrambled pattern-sensitive faults in RAMs

This paper describes a synthesizable, transparent, built-in self-test (BIST) scheme for random-access memories (RAMs). By altering only two parameters in a VHDL specification, BIST circuits can be automatically generated to detect 2-, 3- or 4-cell write-triggered coupling faults as well as two different classes of 5-cell faults. The 5-cell faults represent either unlinked scrambled active physical neighborhood pattern-sensitive faults (PNPSFs), or arbitrary combinations of unlinked scrambled active, static, and passive PNPSFs. The BIST scheme uses a modified version of Nicolaidis´ method to make the applied tests transparent; thus the data that were held in the RAM at the start of the test will be restored by the end of the test, if no faults are present. All single faults of the above fault types, as well as most other standard fault types, are guaranteed to be detected because of the use of an aliasing-free signature analyzer. By comparing numerous intermediate signatures, the new design has a very low probability of aliasing when multiple faults are present