• DocumentCode
    2046780
  • Title

    CMOS Equivalent Model of Ferroelectric RAM

  • Author

    Sandhu, Parvinder S. ; Kaur, Iqbaldeep ; Verma, Amit ; Kalyan, Birinderjit S. ; Kaur, Jagdeep ; Anand, Sanyam

  • Author_Institution
    Deptt. Of CSE, Rayat & Bahra Inst. of Eng. & Bio-Tech., Mohali, India
  • Volume
    1
  • fYear
    2010
  • fDate
    19-21 March 2010
  • Firstpage
    616
  • Lastpage
    620
  • Abstract
    The current research work in the paper is the representation of FRAM (Ferroelectric Random Access Memory) as an equivalent Model of Ferroelectric memory cell in Spice Tool. This Equivalent CMOS based model is designed to work at par with the behaviour working of the FRAM. The crux of the design of ferroelectric capacitor in the Ferroelectric Random Access Memory lies in the Hysteresis loop. Further an analytical comparison of CMOS Model has been done with the existing FRAM Models[1] which are generally Current based. Also,other models and designs that are based on Hysteresis loop have been studied during the research. The designed CMOS Equivalent Model exhibits both the Current and transient Behaviour of the Actual FRAM cell with equally good performance. In Actual Spice tools , FRAM Capacitor is not used, henceforth leads to increase in the complexity of Design and Modeling of FRAM memory in Equivalent CMOS Model.Thus the current research throws light on the detailed and thorough modelling and design of CMOS behavioral Model and CMOS Equivalent Working Model.
  • Keywords
    CMOS memory circuits; ferroelectric capacitors; ferroelectric storage; integrated circuit design; random-access storage; CMOS behavioral model; CMOS equivalent working model; FRAM capacitor; FRAM model; Spice Tool; current behaviour; ferroelectric RAM; ferroelectric capacitor; ferroelectric memory cell; ferroelectric random access memory; hysteresis loop; transient behaviour; Capacitors; Circuits; Ferroelectric films; Ferroelectric materials; Hysteresis; Nonvolatile memory; Polarization; Random access memory; Semiconductor device modeling; Voltage; FRAM; Likewise Dual Capacitor model; the Zero Switching Time Transient Model (ZSTT);
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Engineering and Applications (ICCEA), 2010 Second International Conference on
  • Conference_Location
    Bali Island
  • Print_ISBN
    978-1-4244-6079-3
  • Electronic_ISBN
    978-1-4244-6080-9
  • Type

    conf

  • DOI
    10.1109/ICCEA.2010.282
  • Filename
    5445755