FPGA implementation of a Time Domain Reflectometry (TDR) system for slope monitoring applications

A compact Time Domain Reflectometry (TDR) system was designed and implemented on a Field-Programmable Gate Array (FPGA). The implementation features potential reconfigurability and reprogrammability of important parameters such as pulse shape, pulse width, pulse repetition frequency, and sampling rate. Furthermore, the digital implementation minimizes the need for external analog components. Experimental results of the initial prototype were able to achieve a pulse width of 6.25 ns corresponding to a resolution of 6.67 ns/m in a free space filled cable. We showed that the performance of the system is limited by the conversion rate of the DAC and the maximum clock frequency of the FPGA. However, with advances in FPGAs, ADCs and DACs, this implementation shows tremendous promise in achieving a reconfigurable, flexible, and compact TDR system for slope monitoring.