The implementation of an adaptive bandwidth all-digital phase-locked loop

A circuit architecture of the adaptive-bandwidth all-digital phase-locked lopp (ADB-ADPLL) is designed, where a second-order system with proportional and integral (PI) gains is used to model the ADB-ADPLL. For the implementation of the ADB-PLL, a counter-based phase-frequency detector (PFD) is proposed and a time-to-digital converter (TDC) is used to transform the PFD output to a digital signal. In the ADB-ADPLL system, a digital loop filter (DLF) and a digital-controlled oscillator (DCO) are implemented based on the modulo-N algorithm and PI control. Simulation results are presented to illustrate the ADB-ADPLL performance.