Title :
Parallel Multipliers using 3-Bit-Scan without Overlapping Bits
Author :
Perri, Stefania ; Staino, Giovanni ; Corsonello, Pasquale
Author_Institution :
Dept. of Electron., Comput. Sci. & Syst., Univ. of Calabria, Arcavacata di Rende, Italy
Abstract :
This paper presents a novel high-speed parallel multiplier based on 3-bit-scan without overlapping bits. The proposed multiplier is able to elaborate both signed and unsigned operands and it is suitable for both full-custom and standard-cells based VLSI implementations. When realized using the ST 90 nm CMOS standard-cells library, the 8x8 version of the novel multiplier exhibits a worst-case delay of only 0.93 ns and dissipates ~27 uW/MHz.
Keywords :
CMOS logic circuits; VLSI; digital arithmetic; multiplying circuits; parallel processing; 3-bit-scan without overlapping bits; CMOS standard cells library; VLSI implementations; parallel multipliers; size 90 nm; Adders; CMOS technology; Circuits; Computer science; Digital signal processing; Hardware; Signal processing; Signal processing algorithms; Silicon; Very large scale integration; Digital signal processing; multiplication;
Conference_Titel :
Signal Processing and Communications, 2007. ICSPC 2007. IEEE International Conference on
Conference_Location :
Dubai
Print_ISBN :
978-1-4244-1235-8
Electronic_ISBN :
978-1-4244-1236-5
DOI :
10.1109/ICSPC.2007.4728543
