Parallel Multipliers using 3-Bit-Scan without Overlapping Bits

This paper presents a novel high-speed parallel multiplier based on 3-bit-scan without overlapping bits. The proposed multiplier is able to elaborate both signed and unsigned operands and it is suitable for both full-custom and standard-cells based VLSI implementations. When realized using the ST 90 nm CMOS standard-cells library, the 8x8 version of the novel multiplier exhibits a worst-case delay of only 0.93 ns and dissipates ~27 uW/MHz.