Title :
Leakage power reduction for domino circuits in 45nm CMOS technologies
Author :
Pandey, Akhilesh Kumar ; Kaur, Sukhpreet ; Mishra, R.A. ; Nagaria, R.K.
Author_Institution :
Dept. of Electron. & Commun. Eng., Motilal Nehru Nat. Inst. of Technol., Allahabad, India
Abstract :
A new circuit technique is proposed in this paper for reducing both the subthreshold and gate oxide leakage power in the domino logic circuits. Three high-Vt sleep transistors are added to the standard domino logic circuit to place the circuit into low leakage state. Proposed circuit is evaluated at 110°C and 25°C. At 110°C, proposed circuit reduces leakage power consumption by up to 63%, and at 25°C, it reduces by up to 95.3% as compared to standard dual-Vt domino circuits. Similarly, our proposed circuit reduces leakage power consumption at 110°C by 83.5%, and at 25°C, it reduces up to 95.7% as compared to standard low-Vt domino circuits.
Keywords :
CMOS logic circuits; leakage currents; power consumption; transistor circuits; CMOS technology; circuit technique; gate oxide leakage power reduction; leakage state; size 45 nm; sleep transistor; standard domino logic circuit; subthreshold leakage power consumption reduction; temperature 110 C; temperature 25 C; Dual-Vt; Footed Domino logic; Gate-Oxide Leakage Current; Subthreshold Leakage Current;
Conference_Titel :
Power, Control and Embedded Systems (ICPCES), 2012 2nd International Conference on
Conference_Location :
Allahabad
Print_ISBN :
978-1-4673-1047-5
DOI :
10.1109/ICPCES.2012.6508049
