DocumentCode :
2047129
Title :
Minimizing peak current via opposite-phase clock tree
Author :
Nieh, Yow-Tyng ; Huang, Shih-Hsu ; Hsu, Sheng-Yu
Author_Institution :
Dept. of Electron. Eng., Chung Yuan Christian Univ., Chung Li, Taiwan
fYear :
2005
fDate :
13-17 June 2005
Firstpage :
182
Lastpage :
185
Abstract :
Although a lot of research efforts have been made in the minimization of the total power consumption caused by the clock tree, no attention has been paid to the minimization of the peak current caused by the clock tree. In this paper, we propose an opposite-phase scheme for peak current reduction. Our basic idea is to divide the clock buffers at each level of the clock tree into two sets: an half of clock buffers operate at the same phase of the clock source, and another half of clock buffers operate at the opposite phase of the clock source. Consequently, our approach can reduce the peak current of the clock tree nearly 50%. Experimental data consistently show that our approach works well in practice.
Keywords :
circuit optimisation; clocks; integrated circuit reliability; low-power electronics; network synthesis; clock buffers; clock network synthesis; clock source; low power electronic; opposite-phase clock tree; peak current reduction; power consumption minimization; Capacitance; Circuit noise; Clocks; Energy consumption; Industrial electronics; Minimization; Permission; Power engineering and energy; Power supplies; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2005. Proceedings. 42nd
Print_ISBN :
1-59593-058-2
Type :
conf
DOI :
10.1109/DAC.2005.193797
Filename :
1510316
Link To Document :
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