Title :
A 1.2V 246uW CMOS latched comparator with neutralization technique for reducing Kickback Noise
Author :
Fahmy, Ghazal A. ; Pokharel, R.K. ; Kanaya, H. ; Yoshida, K.
Author_Institution :
Grad. Sch. of Inf. Sci. & Electr. Eng., Kyushu Univ., Fukuoka, Japan
Abstract :
A low power CMOS latched comparator has been designed in TSMC 0.18um employ neutralization technique for reducing Kickback Noise. The simulation results demonstrate that it can work at 1GHz suitable for high speed applications. Measurement results prove that the latched comparator consumes 246uW with a power supply of 1.2v at 10MHz. A simulation method for accurately determining dynamic offset in latched comparator is presented.
Keywords :
CMOS logic circuits; analogue-digital conversion; comparators (circuits); flip-flops; low-power electronics; frequency 1 GHz; frequency 10 MHz; high-speed applications; kickback noise reduction; low-power CMOS latched comparator; neutralization technique; power 246 muW; size 0.18 mum; voltage 1.2 V;
Conference_Titel :
TENCON 2010 - 2010 IEEE Region 10 Conference
Conference_Location :
Fukuoka
Print_ISBN :
978-1-4244-6889-8
DOI :
10.1109/TENCON.2010.5686392
