DocumentCode :
2047202
Title :
Exploiting dynamic reconfiguration techniques: the 2D-VLIW approach
Author :
Santos, Ricardo ; Azevedo, Rodolfo ; Araujo, Guido
Author_Institution :
Inst. of Comput., Campinas State Univ., Sao Paolo, Brazil
fYear :
2006
fDate :
25-29 April 2006
Abstract :
Fast reconfiguration is a mandatory feature for re-configurable computing architectures. Research in this area has been increasingly focusing on new reconfiguration techniques that can sustain the architecture performance and to allow the simultaneous execution, at the same stage, of configuration and computation tasks. In this context, this paper presents a new dynamic reconfiguration technique, based on a configuration cache, that tackles this challenge by configuring and executing operations on functional units during the execution stage. This approach is implemented in a pipelined reconfigurable multiple-issue architecture called 2D-VLIW. Our dynamic reconfiguration technique takes advantage of the 2D-VLIW pipelined execution by starting reconfiguration concurrently to activities like reading operand registers and executing operations.
Keywords :
cache storage; multiprocessing systems; pipeline processing; reconfigurable architectures; 2D-VLIW; configuration cache; dynamic reconfiguration; pipelined reconfigurable multiple-issue architecture; very long instruction word architecture; Computer architecture; Fabrics; Hardware; Pattern recognition; Reconfigurable architectures; Reconfigurable logic; Registers; Runtime; Signal processing; VLIW;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Parallel and Distributed Processing Symposium, 2006. IPDPS 2006. 20th International
Print_ISBN :
1-4244-0054-6
Type :
conf
DOI :
10.1109/IPDPS.2006.1639485
Filename :
1639485
Link To Document :
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