DocumentCode
2047372
Title
Test generation for global delay faults
Author
Luong, G.M. ; Walker, D.M.H.
Author_Institution
Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
fYear
1996
fDate
20-25 Oct 1996
Firstpage
433
Lastpage
442
Abstract
This paper describes test generation for delay faults caused by global process disturbances. The correlations between path delays is used to reduce the number of paths that must be tested. We build macro models of path delays as a function of process parameters to reduce test generation time. The test generation problem is formulated as a nonlinear optimization using a set of candidate paths supplied by a path generator. Results are given for the ISCAS85 benchmarks
Keywords
automatic testing; circuit optimisation; delays; fault diagnosis; integrated circuit modelling; integrated circuit testing; logic testing; IC testing; ISCAS85 benchmarks; global delay faults; logic testing; macro models; nonlinear optimization; path delays; process disturbances; process parameters; test generation; Automatic testing; Benchmark testing; Circuit faults; Circuit testing; Computer science; Delay effects; Integrated circuit testing; Manufacturing processes; Temperature; Time to market;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 1996. Proceedings., International
Conference_Location
Washington, DC
ISSN
1089-3539
Print_ISBN
0-7803-3541-4
Type
conf
DOI
10.1109/TEST.1996.557048
Filename
557048
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