High performance encryption cores for 3G networks

Author

Balderas-Contreras, Tomás ; Cumpliclo, R.

Author_Institution

Inst. Nacional de Astroffsica, Optica y Electronica, Puebla, Mexico

fYear

2005

fDate

13-17 June 2005

Firstpage

240

Lastpage

243

Abstract

This paper presents two novel and high performance hardware architectures, implemented in FPGA technology, for the KASUMI block cipher; this algorithm lies at the core of the confidentiality and integrity algorithms defined for the universal mobile telecommunication system (UMTS) standard. The first proposal is a pipelined design and the second implements an iterative approach. The throughputs for these architectures turn out to be higher than the throughput achieved by other proposals.

Keywords

3G mobile communication; cryptography; field programmable gate arrays; pipeline processing; telecommunication security; 3G networks; FPGA technology; KASUMI block cipher; UMTS standard; confidentiality algorithms; encryption cores; hardware architectures; integrity algorithms; iterative approach; pipelined design; security architecture; universal mobile telecommunication system; 3G mobile communication; Clocks; Cryptography; Data security; Field programmable gate arrays; Iterative algorithms; Iterative methods; Permission; Pipelines; Proposals;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2005. Proceedings. 42nd

Print_ISBN

1-59593-058-2

Type

conf

DOI

10.1109/DAC.2005.193808

Filename

1510327

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2047399