DocumentCode :
2047469
Title :
Simulation based deadlock analysis for system level designs
Author :
Chen, Xi ; Davare, Abhijit ; Hsieh, Harry ; Sangiovanni-Vincentelli, Alberto ; Watanabe, Yosinori
Author_Institution :
California Univ., Riverside, CA, USA
fYear :
2005
fDate :
13-17 June 2005
Firstpage :
260
Lastpage :
265
Abstract :
In the design of highly complex, heterogeneous, and concurrent systems, deadlock detection and resolution remains an important issue. In this paper, we systematically analyze the synchronization dependencies in concurrent systems modeled in the Metropolis design environment, where system functions, high level architectures and function-architecture mappings can be modeled and simulated. We propose a data structure called the dynamic synchronization dependency graph, which captures the runtime (blocking) dependencies. A loop-detection algorithm is then used to detect deadlocks and help designers quickly isolate and identify modeling errors that cause the deadlock problems. We demonstrate our approach through a real world design example, which is a complex functional model for video processing and a high level model of function-architecture mapping.
Keywords :
electronic engineering computing; high level synthesis; integrated circuit design; systems analysis; Metropolis design; complex functional model; concurrent systems model; data structure; deadlock analysis; deadlock detection; dynamic synchronization dependency graph; function-architecture mappings; high level architectures; loop-detection algorithm; modeling errors; runtime dependencies; system functions; system level designs; video processing; Algorithm design and analysis; Analytical models; Computer architecture; Data structures; Laboratories; Modems; Permission; Runtime; System recovery; System-level design;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2005. Proceedings. 42nd
Print_ISBN :
1-59593-058-2
Type :
conf
DOI :
10.1109/DAC.2005.193812
Filename :
1510331
Link To Document :
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