DocumentCode :
2047476
Title :
ATPD: an automatic test pattern generator for path delay faults
Author :
Karayiannis, D. ; Tragoudas, S.
Author_Institution :
Dept. of Comput. Sci., Southern Illinois Univ., Carbondale, IL, USA
fYear :
1996
fDate :
20-25 Oct 1996
Firstpage :
443
Lastpage :
452
Abstract :
In this paper we present an efficient test pattern generator for robust path delay faults, which we call ATPD. Our CAD tool detects much faster more robust path delay faults than any other existing nonenumerative approach. ATPD generates patterns for a non necessarily polynomial number of path delay faults. The nature of the problem indicates that for a test generator to be efficient it must count nonenumeratively the additional delay paths detected by each generated pair of patterns. ATPD generates each pair of patterns and determines the number of paths covered in a novel way that combines these two phases effectively
Keywords :
automatic testing; delays; fault diagnosis; integrated circuit testing; logic CAD; logic testing; polynomials; ATPD; CAD tool; automatic test pattern generator; nonenumerative count; path delay faults; polynomial number; test generator; Character generation; Circuit faults; Circuit testing; Computer science; Delay effects; Electrical fault detection; Fault detection; Polynomials; Robustness; Test pattern generators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference, 1996. Proceedings., International
Conference_Location :
Washington, DC
ISSN :
1089-3539
Print_ISBN :
0-7803-3541-4
Type :
conf
DOI :
10.1109/TEST.1996.557051
Filename :
557051
Link To Document :
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