• DocumentCode
    2047495
  • Title

    Fault and energy-aware communication mapping with guaranteed latency for applications implemented on NoC

  • Author

    Manolache, Sorin ; Eles, Petru ; Peng, Zebo

  • Author_Institution
    Linkoping Univ., Sweden
  • fYear
    2005
  • fDate
    13-17 June 2005
  • Firstpage
    266
  • Lastpage
    269
  • Abstract
    As feature sizes shrink, transient failures of on-chip network links become a critical problem. At the same time, many applications require guarantees on both message arrival probability and response time. We address the problem of transient link failures by means of temporally and spatially redundant transmission of messages, such that designer-imposed message arrival probabilities are guaranteed. Response time minimisation is achieved by a heuristic that statically assigns multiple copies of each message to network links, intelligently combining temporal and spatial redundancy. Concerns regarding energy consumption are addressed in two ways. Firstly, we reduce the total amount of transmitted messages, and, secondly, we minimise the application response time such that the resulted time slack can be exploited for energy savings through voltage reduction. The advantages of the proposed approach are guaranteed message arrival probability and guaranteed worst case application response time.
  • Keywords
    computer architecture; directed graphs; integrated circuit design; integrated circuit reliability; integrated circuit testing; network analysis; system-on-chip; NoC; energy consumption; energy-aware communication mapping; fault communication mapping; message arrival probability; on-chip network links; redundant messages transmission; response time minimisation; spatial redundancy; temporal redundancy; transient link failures; Context; Data communication; Delay; Energy consumption; Hardware; Intelligent networks; Network-on-a-chip; Telecommunication network reliability; Testing; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 2005. Proceedings. 42nd
  • Print_ISBN
    1-59593-058-2
  • Type

    conf

  • DOI
    10.1109/DAC.2005.193813
  • Filename
    1510332