Test vector generation for parametric path delay faults

Previous research in the field of path delay fault test generation has concentrated on finding tests which test paths regardless of component delay values. Coverage of such tests on benchmark circuits has been shown to be poor so we present a mechanism wherein path delay fault tests are found under the assumption of component delay variations resulting from fabrication process fluctuations. Component delay fault models are built which incorporate fabrication process effects represented in terms of basic process parameter variations. We use a sensitization approach based on signal stabilizing times to get conditions on primary inputs and path delays for which a delay fault is produced at the circuit outputs. A minimal test set is then extracted from these conditions. Results for the ISCAS´89 and Logic synthesis´91 benchmark circuits indicate the feasibility of this approach