• DocumentCode
    2047725
  • Title

    An efficient algorithm for statistical minimization of total power under timing yield constraints

  • Author

    Mani, Murari ; Devgan, Anirudh ; Orshansky, Michael

  • Author_Institution
    Texas Univ., Austin, TX, USA
  • fYear
    2005
  • fDate
    13-17 June 2005
  • Firstpage
    309
  • Lastpage
    314
  • Abstract
    Power minimization under variability is formulated as a rigorous statistical robust optimization program with a guarantee of power and timing yields. Both power and timing metrics are treated probabilistically. Power reduction is performed by simultaneous sizing and dual threshold voltage assignment. An extremely fast run-time is achieved by casting the problem as a second-order conic problem and solving it using efficient interior-point optimization methods. When compared to the deterministic optimization, the new algorithm, on average, reduces static power by 31% and total power by 17% without the loss of parametric yield. The run time on a variety of public and industrial benchmarks is 30× faster than other known statistical power minimization algorithms.
  • Keywords
    circuit optimisation; integrated circuit design; low-power electronics; minimisation; conic problem; deterministic optimization; dual threshold voltage assignment; interior-point optimization methods; power reduction; sizing assignment; statistical power minimization algorithms; timing yield constraints; Algorithm design and analysis; Circuits; Constraint optimization; Design optimization; Manufacturing processes; Minimization methods; Optimization methods; Robustness; Threshold voltage; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 2005. Proceedings. 42nd
  • Print_ISBN
    1-59593-058-2
  • Type

    conf

  • DOI
    10.1109/DAC.2005.193823
  • Filename
    1510342