DocumentCode :
2047770
Title :
Multiple-fault detection for the balanced and unbalanced conditional-sum adders
Author :
Arjhan, Chanyutt ; Deshmukh, Raghvendra G.
Author_Institution :
Div. of Electr. & Comput. Sci. & Eng., Florida Inst. of Technol., Melbourne, FL, USA
fYear :
2000
fDate :
2000
Firstpage :
359
Lastpage :
364
Abstract :
In this paper the pair-fault (pf) model (Arjhan and Deshmukh 1998), its concept of multiple fault boundaries (MFBs) and fault-dominance are applied to detect multiple stuck-at faults of the conditional-sum type adders´ carry-tree. There are 2n+1 test patterns (n is the operand width) to be applied through the primary inputs of the carry binary-trees. The tree can be balanced or unbalanced. For this purpose, the architecture of the adders is reformulated such that they will correspond to the parallel-prefix lookahead adders and the proof of testability is then followed
Keywords :
adders; carry logic; integrated circuit testing; integrated logic circuits; logic testing; trees (mathematics); 2n+1 test patterns; architecture; balanced conditional-sum adders; carry binary-trees; conditional-sum type adders carry-tree; fault-dominance; multiple fault boundaries; multiple stuck-at faults; multiple-fault detection; pair-fault model; parallel-prefix lookahead adders; primary inputs; testability; unbalanced conditional-sum adders; Computer science; Delay; Electrical fault detection; Fault detection; Robustness; Testing; Upper bound;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Southeastcon 2000. Proceedings of the IEEE
Conference_Location :
Nasville, TN
Print_ISBN :
0-7803-6312-4
Type :
conf
DOI :
10.1109/SECON.2000.845593
Filename :
845593
Link To Document :
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