Test generation and design for test for a large multiprocessing DSP

Author

Hetherington, Graham ; Sutton, Greg ; Butler, Kenneth M. ; Powell, Theo J.

Author_Institution

Texas Instrum. Ltd., Northampton, UK

fYear

1995

fDate

21-25 Oct 1995

Firstpage

149

Lastpage

156

Abstract

The TMS320C80 is a programmable, parallel processing DSP. The test approach was an engineering mix of design for testability, test view creation, and verification. This mixture facilitated timely test generation and had other important benefits. We document the overall test methodology and the benefits derived therein

Keywords

CMOS digital integrated circuits; automatic testing; boundary scan testing; circuit analysis computing; design for testability; digital signal processing chips; fault diagnosis; high level synthesis; integrated circuit design; integrated circuit testing; logic testing; parallel architectures; reduced instruction set computing; ATPG; JTAG; MIMD architecture; TMS320C80; automated failure diagnosis; design for testability; embedded RISC master processor; high level test architecture; large multiprocessing DSP; multimedia video processor; programmable parallel processing DSP; test methodology; test view creation; timely test generation; verification; Automatic test pattern generation; Automatic testing; Costs; Design engineering; Design for testability; Digital signal processing; Instruments; Multimedia systems; Parallel processing; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1995. Proceedings., International

Conference_Location

Washington, DC

ISSN

1089-3539

Print_ISBN

0-7803-2992-9

Type

conf

DOI

10.1109/TEST.1995.529828

Filename

529828