Towards an effective IDDQ test vector selection and application methodology

We show that that for a complex CLSI (1.4 M transistor used in the Asymmetric Digital Subscriber Line product range), 632 I_DDQ measurements are needed to obtain 94% pseudo stuck-at fault coverage. The I_DDQ test takes less than 200 ms on the VLSI test system, which is between 100 to 300 times faster compared to the use of a PMU. In addition, the OCIMU I_DDQ monitor is built into our VLSI test system allowing I_DDQ tests at wafer level without placing active components on the load board. This I_DDQ methodology applies many I_DDQ vectors, achieves a high fault coverage and is feasible in a production environment. Correlation between functional failures and I_DDQ failures is around 70% for three CLSI designs. Extrapolation implies that the slip-through (i.e. bad devices that pass all tests) can be reduced by 70% by augmenting the test program with an I_DDQ test. As a consequence, the non-quality costs can be reduced significantly depending on the slip-through figures, component and repair costs